This invention relates generally to computer memory, and more specifically to non-volatile memories with enhanced write performance and endurance.
Phase-change memories (PCMs) and flash memories are examples of non-volatile memories with limited endurance (also referred to as a “limited life”). Such memories have limited endurance in the sense that after undergoing a number of writing cycles (RESET cycles for PCM, program/erase cycles for flash memory), the memory cells wear out and can no longer reliably store information.
One characteristic of contemporary not-and (NAND) flash memory devices is that they do not support page erase. The absence of page erases implies that once a page is written, it is not rewritten until the entire block (e.g. made up of sixty-four pages) is erased. Conventional memory systems having NAND flash memory devices employ log-structured file systems, where physical page addresses are different from logical page addresses, and a mapping of logical to physical page addresses is maintained. When a write to a logical address first appears it is allocated to a free (erased) page and the logical-to-physical mapping is stored. Subsequently, if the data at the logical address is to be updated, a new erased block is used for writing the data, the logical-to-physical map corresponding to the logical address is updated, and the earlier physical page is marked as invalid.
In order to avoid running out of writable pages, a periodic process, referred to as “garbage collection” is performed. During garbage collection, the valid pages from one or more blocks are moved to free pages and the blocks are then erased. Since this process involves freeing up invalid pages, it allows the memory device to regain previously programmed (or written) pages. However, the process of garbage collection generates additional writes (i.e. writes which are not directly used for writing data corresponding to a logical address to memory). These extra writes can increase system latency (because, in general, NAND programming operations have a high latency) and can reduce system endurance (because a NAND cell wears out after undergoing a limited number of program-erase cycles).